Course Introduction and Application Information

Course Code:

COE302

Course Name:

Computer Architecture

Semester:

Fall

Course Credits:

ECTS

Language of instruction:

English

Course Condition:

Does the Course Require Work Experience?:

Type of course:

Compulsory Courses

Course Level:

Bachelor

TR-NQF-HE:6. Master`s Degree

QF-EHEA:First Cycle

EQF-LLL:6. Master`s Degree

Mode of Delivery:

Face to face

Course Coordinator:

Doç. Dr. AMIR SEYYEDABBASI

Course Lecturer(s):

Assist. Prof. Dr. Hüsamettin OSMANOĞLU

Course Assistants:

Course Objective and Content

Course Objectives:	This course covers computer architecture and techniques for improving performance, including pipelining, instruction-level parallelism, memory hierarchy design, and multithreading. It emphasizes hardware-software interaction and includes compiler and operating system-related topics.
Course Content:	CPU and Instruction set architectures. Memory Hierarchy and Model, including registers, cache memory, main memory (RAM) and Hard Disk. Arithmetic and Logic including Digital logic, digital systems, digital design, Number Systems and Computer Arithmetic. Instruction Sets and Assembly Language such as MIPS Characteristics and Functions, Addressing Modes and Formats. RISC and CISC architecture.

Learning Outcomes

The students who have succeeded in this course;
1) Understand the basics of computers and how they are organized in terms of hardware and software: the importance of the hardware-software interface.
2) Understand various key components of a computer–such as memory, interfaces, processor, I/O, cache memory, ALU, RISC and CISC machine, interrupts, pipelining, instruction-level parallelism, and memory hierarchy design.
3) Develop proficiency in different types of instruction set architectures, specifically focusing on the MIPS instruction set and MIPS assembly language, and acquire the ability to compare and contrast various instruction set architectures for specific functions.
4) Acquire the skills to design a datapath and control unit for a pipelined processor through single-cycle implementation techniques and demonstrate the capability to design and implement a simple processor using fundamental elements such as combinational logic, memory components, and other essential units.

Course Flow Plan

Week	Subject	Related Preparation
1)	Basic Concepts and Computer Evolution
2)	Performance Concepts
3)	A Top-Level View of Computer Function and Interconnection
4)	Main Memory
5)	Cache Memory
6)	Input/output and Interrupts
7)	Operating System Support
8)	Midterm
9)	Computer Arithmetic
10)	Instruction Sets: Characteristics and Functions
11)	Addressing Modes and Formats
12)	Introduction to MIPS instruction ser
13)	Reduced Instruction Set Computers
14)	Processor Pipeline, Structure and Function

Sources

Course Notes / Textbooks:

William Stallings - Computer Organization and Architecture, Global Edition (2021, Pearson)

References:

[1] David A. Patterson, John L. Hennessy - Computer Organization and Design: The Hardware_Software Interface 5th Edition
[2] M. Morris Mano. Digital Logic and Computer Design.-Pearson (2017)
[3] Morgan Kaufmann Publishers._Harris, David Money_Harris, Sarah L - Digital design and computer architecture-Elsevier_Morgan Kaufmann Publishers (2018)
[4] http://williamstallings.com/ComputerOrganization/COA11e/

Course - Program Learning Outcome Relationship

Course Learning Outcomes	1	2	3	4
Program Outcomes

Course - Learning Outcome Relationship

No Effect	1 Lowest	2 Average	3 Highest

Program Outcomes

Level of Contribution

Assessment & Grading

Semester Requirements	Number of Activities	Level of Contribution
Quizzes	4	% 10
Homework Assignments	5	% 20
Midterms	1	% 30
Final	1	% 40
total		% 100
PERCENTAGE OF SEMESTER WORK		% 60
PERCENTAGE OF FINAL WORK		% 40
total		% 100

Workload and ECTS Credit Calculation

Activities	Number of Activities	Workload
Course Hours	13	39
Study Hours Out of Class	13	39
Homework Assignments	5	10
Quizzes	4	12
Midterms	1	20
Final	1	30
Total Workload		150